The APL5333 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown into a single chip.

Features3I2嘉泰姆

Sourcing and Sinking Current up to 3A3I2嘉泰姆

Wide Input Voltage Range: 1.2V to 3.6V3I2嘉泰姆

VTT and VTTREF Voltage Tracks at Half the3I2嘉泰姆

VREF Voltage3I2嘉泰姆

VTT and VTTREF Voltage with ±20mV Accuracy3I2嘉泰姆

Excellent Load Transient Response3I2嘉泰姆

- Droop Compensation3I2嘉泰姆

- Fast Loop Response3I2嘉泰姆

Stable with 20µF Ceramic Output Capacitors3I2嘉泰姆

Current Limit Protection3I2嘉泰姆

Thermal Shutdown Protection3I2嘉泰姆

Power-On-Reset Function on VCNTL3I2嘉泰姆

S3, S5 Input Signals for ACPI States3I2嘉泰姆

Available in a Thermal Enhanced MSOP-10P3I2嘉泰姆

Package3I2嘉泰姆

Lead Free Available (RoHS Compliant)3I2嘉泰姆

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General Description 3I2嘉泰姆

The APL5333 linear regulator is designed to provide a3I2嘉泰姆

regulated voltage with bi-directional output current for3I2嘉泰姆

DDR-SDRAM termination. The APL5333 integrates two3I2嘉泰姆

power transistors to source or sink current up to 3A. It3I2嘉泰姆

also incorporate current-limit, thermal shutdown into a3I2嘉泰姆

single chip.3I2嘉泰姆

The output voltage of APL5333 tracks the voltage at VREF3I2嘉泰姆

pin. An internal resistor divider is used to provide a half3I2嘉泰姆

voltage of VREF for VTTREF and VTT Voltage. The VTT3I2嘉泰姆

output voltage is only requiring 20µF of ceramic output3I2嘉泰姆

capacitance for stability and fast transient response. The3I2嘉泰姆

S3 and S5 pins provide the sleep state for VTT (S3 state)3I2嘉泰姆

and suspend state (S4/S5 state) for device, when S5 and3I2嘉泰姆

S3 are both pulled low the device provides the soft-off for3I2嘉泰姆

VTT and VTTREF. The MSOP-10P package with a copper3I2嘉泰姆

pad is available which provides excellent thermal3I2嘉泰姆

impedance.3I2嘉泰姆

Simplified Application Circuit3I2嘉泰姆

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相关文件3I2嘉泰姆

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