CXSD62102 is a single-phase, constant on-time, synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102 steps down high voltage to generate low-voltage chipset or RAM supplies in no

发布时间：2020-04-06 09:43:38 浏览次数：703 作者：嘉泰姆来源：1

摘要：CXSD62102 is a single-phase, constant on-time, synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102 steps down high voltage to generate low-voltage chipset or RAM supplies in no

目录7uS嘉泰姆

1.产品概述 2.产品特点
3.应用范围 4.下载产品资料PDF文档
5.产品封装图 6.电路原理图
7.功能概述 8.相关产品7uS嘉泰姆

一,产品概述(General Description)
The CXSD62102 is a single-phase, constant on-time, synchronous PWM
controller, which drives N-channel MOSFETs. The CXSD62102 steps down high
voltage to generate low-voltage chipset or RAM supplies in notebook computers.
The CXSD62102 provides excellent transient response and accurate DC voltage
output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), theCXSD62102 provides very high efficiency over light to heavy loads with loading-
modulated switching frequencies. In PWM Mode, the converter works nearly at
constant frequency for low-noise requirements. CXSD62102 is built in remote
sense function for applications that require remote sense.The CXSD62102 is
equipped with accurate positive current limit, output under-voltage, and output
over-voltage protections, perfect for NB applications. The Power-On-Reset
function monitors the voltage on VCC to prevent wrong operation during
power-on. The CXSD62102 has a 1ms digital soft start and built-in an integrated
output discharge device for soft stop. An internal integrated soft-start ramps up
the output voltage with programmable slew rate to reduce the start-up current.
A soft-stop function actively discharges the output capacitors.
The CXSD62102 is available in 16pin TQFN3x3-16 package respectively.
二.产品特点(Features)
1.)Adjustable Output Voltage from +0.6V to +3.3V
- 0.6V Reference Voltage
- ±0.6% Accuracy Over-Temperature
2.)Operates from An Input Battery Voltage Range of +1.8V to +28V
3.)Remote Feedback Sense for Excellent Output Voltage
4.)REFIN Function for Over-clocking Purpose from 0.5V~2.5V range
5.)Power-On-Reset Monitoring on VCC pin
6.)Excellent line and load transient responses
7.)PFM mode for increased light load efficiency
8.)Programmable PWM Frequency from 100kHz to 500kHz
9.)Selectable Forced PWM or automatic PFM/PWM mode
10.)Built in 30A Output current driving capabilityIntegrate MOSFET Drivers
11.)Integrated Bootstrap Forward P-CH MOSFET
12.)Adjustable Integrated Soft-Start and Soft-Stop Power Good Monitoring
13.)70% Under-Voltage Protection
14.)125% Over-Voltage Protection TQFN3x3-16 Package
15.)Lead Free and Green Devices Available
三,应用范围 (Applications)
Notebook
Table PC
Hand-Held Portable
AIO PC
四.下载产品资料PDF文档 7uS嘉泰姆

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QQ截图20160419174301.jpg 7uS嘉泰姆

五,产品封装图 (Package)7uS嘉泰姆

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六.电路原理图7uS嘉泰姆

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七,功能概述7uS嘉泰姆

Input Capacitor Selection (Cont.)
higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2,where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current.For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be-tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout.
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET.
In the turning off process of the low-side MOSFET, the load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capaci-tor through the low-side MOSFET driver sinking current path. This results in much less switching
loss of the low-side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con-verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. The high-side MOSFET does not have this zero voltage switch-ing condition; in addition, it conducts for less time com-pared to the low-side MOSFET, so the switching loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci-tance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately
given by the following equations:
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) is the load current TC is the temperature dependency of RDS(ON)
FSW is the switching frequency tSW is the switching interval D is the duty cycleNote that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss.The switching interval, tSW, is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET.
Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-rating and finally combined using ground plane construc-
tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega-
tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not
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CXSD621057uS嘉泰姆	TQFN4x4-247uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	157uS嘉泰姆	67uS嘉泰姆	257uS嘉泰姆	27uS嘉泰姆	N7uS嘉泰姆	5507uS嘉泰姆
CXSD62106\|A7uS嘉泰姆	TQFN4x4-47uS嘉泰姆 TQFN3x3-207uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	207uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	8007uS嘉泰姆
CXSD621077uS嘉泰姆	TQFN3x3-167uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	17uS嘉泰姆	207uS嘉泰姆	1.87uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	4007uS嘉泰姆
CXSD621087uS嘉泰姆	QFN3.5x3.5-147uS嘉泰姆 TQFN3x3-167uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	17uS嘉泰姆	207uS嘉泰姆	1.87uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	4007uS嘉泰姆
CXSD621097uS嘉泰姆	TQFN3x3-167uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	207uS嘉泰姆	1.87uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	4007uS嘉泰姆
CXSD621107uS嘉泰姆	QFN3x3-207uS嘉泰姆 TQFN3x3-167uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	207uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	1.8\|1.5\|0.57uS嘉泰姆	57uS嘉泰姆	7407uS嘉泰姆
CXSD621117uS嘉泰姆	TQFN4x4-247uS嘉泰姆 \|QFN3x3-207uS嘉泰姆	CM7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	157uS嘉泰姆	57uS嘉泰姆	287uS嘉泰姆	0.57uS嘉泰姆	N7uS嘉泰姆	30007uS嘉泰姆
CXSD621127uS嘉泰姆	TDFN3x3-107uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	17uS嘉泰姆	207uS嘉泰姆	1.87uS嘉泰姆	287uS嘉泰姆	0.57uS嘉泰姆	57uS嘉泰姆	2507uS嘉泰姆
CXSD62113\|C7uS嘉泰姆	TQFN3x3-207uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	157uS嘉泰姆	67uS嘉泰姆	257uS嘉泰姆	27uS嘉泰姆	N7uS嘉泰姆	5507uS嘉泰姆
CXSD62113E7uS嘉泰姆	TQFN 3x3 207uS嘉泰姆	COT7uS嘉泰姆	27uS嘉泰姆	27uS嘉泰姆	117uS嘉泰姆	67uS嘉泰姆	257uS嘉泰姆	27uS嘉泰姆	N7uS嘉泰姆	5507uS嘉泰姆
CXSD621147uS嘉泰姆	TQFN3x3-207uS嘉泰姆	COT7uS嘉泰姆	27uS嘉泰姆	27uS嘉泰姆	117uS嘉泰姆	5.57uS嘉泰姆	257uS嘉泰姆	27uS嘉泰姆	N7uS嘉泰姆	2807uS嘉泰姆
CXSD621157uS嘉泰姆	QFN4x4-247uS嘉泰姆	VM7uS嘉泰姆	27uS嘉泰姆	17uS嘉泰姆	607uS嘉泰姆	3.17uS嘉泰姆	13.27uS嘉泰姆	0.857uS嘉泰姆	127uS嘉泰姆	50007uS嘉泰姆
CXSD62116A\|B\|C7uS嘉泰姆	SOP-8P7uS嘉泰姆	VM7uS嘉泰姆	17uS嘉泰姆	17uS嘉泰姆	207uS嘉泰姆	2.97uS嘉泰姆	13.27uS嘉泰姆	0.87uS嘉泰姆	127uS嘉泰姆	160007uS嘉泰姆
CXSD621177uS嘉泰姆	SOP-207uS嘉泰姆	VM7uS嘉泰姆	27uS嘉泰姆	27uS嘉泰姆	307uS嘉泰姆	107uS嘉泰姆	13.27uS嘉泰姆	17uS嘉泰姆	127uS嘉泰姆	50007uS嘉泰姆
CXSD621187uS嘉泰姆	TDFN3x3-107uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	17uS嘉泰姆	257uS嘉泰姆	1.87uS嘉泰姆	287uS嘉泰姆	0.77uS嘉泰姆	57uS嘉泰姆	2507uS嘉泰姆
CXSD621197uS嘉泰姆	TQFN3x3-207uS嘉泰姆	COT7uS嘉泰姆	27uS嘉泰姆	17uS嘉泰姆	407uS嘉泰姆	1.87uS嘉泰姆	257uS嘉泰姆	REFIN Setting7uS嘉泰姆	57uS嘉泰姆	7007uS嘉泰姆
CXSD621207uS嘉泰姆	QFN 3x3 207uS嘉泰姆 TQFN 3x3 167uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	207uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	1.8\|1.5 1.35\|1.2 0.57uS嘉泰姆	57uS嘉泰姆	8007uS嘉泰姆
CXSD62121A7uS嘉泰姆	TQFN3x3 207uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	157uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	2207uS嘉泰姆
CXSD62121B7uS嘉泰姆	TQFN3x3 207uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	157uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	2207uS嘉泰姆
CXSD621217uS嘉泰姆	TQFN3x3-207uS嘉泰姆	COT7uS嘉泰姆	17uS嘉泰姆	27uS嘉泰姆	207uS嘉泰姆	37uS嘉泰姆	287uS嘉泰姆	0.757uS嘉泰姆	57uS嘉泰姆	1807uS嘉泰姆

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CXSD62102 is a single-phase, constant on-time, synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102 steps down high voltage to generate low-voltage chipset or RAM supplies in no

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CXSD62102 is a single-phase, constant on-time, synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102 steps down high voltage to generate low-voltage chipset or RAM supplies in no

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