CXSD62100电压模式固定300kHz开关频率同步降压变换器上电复位（POR）电路监测VCC电源电压，以防止错误的逻辑控制。内置的软启动电路可防止输出电压过冲，并限制输入电流

目录EZJ嘉泰姆

1.产品概述                       2.产品特点EZJ嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 EZJ嘉泰姆
5.产品封装图                     6.电路原理图                   EZJ嘉泰姆
7.功能概述                        8.相关产品EZJ嘉泰姆

一,产品概述(General Description)     EZJ嘉泰姆

           The CXSD62100 is a voltage mode, fixed 300kHz witching frequency, synchronous buck converter. The CXSD62100 allows wide input voltage that is either a single 5~12V or two supply voltage(s) for various applications. A power-on-reset (POR) circuit monitors the VCC supply voltage to prevent wrong logic controls. A built-in soft-start circuit prevents the output voltages from overshoot as well as limits the input current. An internal 0.6V temperature-com-pensated reference voltage with high accuracy is de-signed to meet the requirement of low output voltage applications. The CXSD62100 provides excellent output volt-age regulations against load current variation. CXSD62100 is built in remote sense function for applications that re-quire remote sense. (TDFN-10 3mmx3mm Package Only)The controller’s over-current protection monitors the out-put current by using the voltage drop across the RDS (ON) of low-side MOSFET, eliminating the need for a cur-rent sensing resistor that features high efficiency and low cost. In addition, the CXSD62100 also integrates excel-lent protection functions. The over-voltage protection (OVP) , under-voltage protection (UVP). OVP circuit which moni-tors the FB voltage to prevent the PWM output from over voltage, and UVP circuit which monitors the FB voltage to prevent the PWM output from under voltage or short circuit.EZJ嘉泰姆
       The CXSD62100 is available in TDFN3x3-10 packagesEZJ嘉泰姆
二.产品特点(Features)EZJ嘉泰姆

1.）Wide 5V to 12V Supply VoltageEZJ嘉泰姆
2.）Power-On-Reset Monitoring on VCCEZJ嘉泰姆
3.）Excellent Output Voltage RegulationsEZJ嘉泰姆
      - 0.6V Internal ReferenceEZJ嘉泰姆
      - ±0.6% Over-Temperature RangeEZJ嘉泰姆
4.）Integrated Soft-StartEZJ嘉泰姆
5.）Voltage Mode PWM Operation with External CompensationEZJ嘉泰姆
6.）Up to 90% Duty Ratio for Fast Transient ResponseEZJ嘉泰姆
7.）Constant Switching Frequency - 300kHz ±10%EZJ嘉泰姆
8.）Integrated Bootstrap Forward P-CH MOSFETEZJ嘉泰姆
9.）50% Under-Voltage ProtectionEZJ嘉泰姆
10.）125% Over-Voltage ProtectionEZJ嘉泰姆
11.）Adjustable Over-Current Protection ThresholdEZJ嘉泰姆
      - Using the RDS(ON) of Low-Side MOSFETEZJ嘉泰姆
12.）Shutdown Control by COMPEZJ嘉泰姆
13.）Power Good Monitoring (TDFN-10 3mmx3mm Package Only)EZJ嘉泰姆
14.）Remote Feedback Sense for Excellent OutputEZJ嘉泰姆
15.）Voltage (TDFN-10 3mmx3mm Package Only) TDFN3x3-10 PackageEZJ嘉泰姆
16.）Lead Free and Green Devices AvailableEZJ嘉泰姆
三,应用范围 (Applications)EZJ嘉泰姆

Graphic CardsEZJ嘉泰姆
DSL, Switch HUBEZJ嘉泰姆
Wireless LanEZJ嘉泰姆
Notebook ComputerEZJ嘉泰姆
Mother BoardEZJ嘉泰姆
LCD Monitor/TVEZJ嘉泰姆
四.下载产品资料PDF文档 EZJ嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！EZJ嘉泰姆

 EZJ嘉泰姆

五,产品封装图 (Package)EZJ嘉泰姆

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六.电路原理图EZJ嘉泰姆

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七,功能概述EZJ嘉泰姆

Layout ConsiderationEZJ嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of theEZJ嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike acrossEZJ嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionEZJ嘉泰姆
of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off, current stopsEZJ嘉泰姆
flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance ofEZJ嘉泰姆
the circuit generates a large voltage spike during the switching interval. In general, using short and wide printedEZJ嘉泰姆
circuit traces should minimize interconnecting imped ances and the magnitude of voltage spike. And signalEZJ嘉泰姆
and power grounds are to be kept separate till combined using ground plane construction or single pointEZJ嘉泰姆
grounding. Figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be shortEZJ嘉泰姆
and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout:EZJ嘉泰姆
- Keep the switching nodes (UGATE, LGATE, and PHASE)away from sensitive small signal nodes since theseEZJ嘉泰姆
nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.EZJ嘉泰姆
- The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide.EZJ嘉泰姆
- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-EZJ嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.EZJ嘉泰姆
- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closeEZJ嘉泰姆
their pins. (For example, place the decoupling ceramiccapacitor near the drain of the high-side MOSFET asEZJ嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).EZJ嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near theEZJ嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.EZJ嘉泰姆
 The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.EZJ嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.EZJ嘉泰姆

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