2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

发布时间:2020-06-08 08:20:13 浏览次数:343 作者:oumao18 来源:嘉泰姆
摘要:CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度
2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

目录sYd嘉泰姆

1.产品概述                       2.产品特点sYd嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 sYd嘉泰姆
5.产品封装图                     6.电路原理图                   sYd嘉泰姆
7.功能概述                        8.相关产品sYd嘉泰姆

一,产品概述(General Description)         sYd嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.sYd嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.sYd嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withsYd嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slewsYd嘉泰姆
rate. All inputs and outputs are rail-to-rail.sYd嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).sYd嘉泰姆
二.产品特点(Features)sYd嘉泰姆


· 2.6V to 6.5V Input Supply Range sYd嘉泰姆

· Current-Mode Step-Up Regulator sYd嘉泰姆

 - Fast Transient Response sYd嘉泰姆

 - 1.2MHz Fixed Operating Frequency sYd嘉泰姆

· ±1.5% High-Accuracy Output Voltage sYd嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET sYd嘉泰姆

· High Efficiency sYd嘉泰姆

· Low Quiescent Current (0.6mA Typical) sYd嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF sYd嘉泰姆

· High-performance Operational Amplifiers sYd嘉泰姆

 - ±150mA Output Short-Circuit CurrentsYd嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth sYd嘉泰姆

 - Rail-to-Rail Inputs/Outputs sYd嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs sYd嘉泰姆

· Over-Temperature Protection sYd嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) sYd嘉泰姆

· Lead Free Available (RoHS Compliant)sYd嘉泰姆

三,应用范围 (Applications)sYd嘉泰姆


    TFT LCD Displays for MonitorssYd嘉泰姆
   TFT LCD Displays for Notebook ComputerssYd嘉泰姆
   Automotive DisplayssYd嘉泰姆
四.下载产品资料PDF文档 sYd嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持sYd嘉泰姆

 QQ截图20160419174301.jpgsYd嘉泰姆

五,产品封装图 (Package)sYd嘉泰姆


blob.pngsYd嘉泰姆
blob.pngPin Function DescriptionsYd嘉泰姆

PinsYd嘉泰姆

NamesYd嘉泰姆

Function DescriptionsYd嘉泰姆

CXSU63137sYd嘉泰姆

CXSU63137-1sYd嘉泰姆

CXSU63137-2sYd嘉泰姆

1sYd嘉泰姆

SRCsYd嘉泰姆

SRCsYd嘉泰姆

SRCsYd嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. BypasssYd嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.sYd嘉泰姆

2sYd嘉泰姆

REFsYd嘉泰姆

REFsYd嘉泰姆

REFsYd嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofsYd嘉泰姆
0.22μFcapacitor closed to the pins.sYd嘉泰姆

3sYd嘉泰姆

AGNDsYd嘉泰姆

AGNDsYd嘉泰姆

AGNDsYd嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect tosYd嘉泰姆
power ground (PGND) underneath the IC.sYd嘉泰姆

4sYd嘉泰姆

PGNDsYd嘉泰姆

PGNDsYd嘉泰姆

PGNDsYd嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-upsYd嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputsYd嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog groundsYd嘉泰姆
(AGND) underneath the IC.sYd嘉泰姆

5sYd嘉泰姆

OUT1sYd嘉泰姆

OUT1sYd嘉泰姆

OUT1sYd嘉泰姆

Output of Operational-Amplifier 1sYd嘉泰姆

6sYd嘉泰姆

NEG1sYd嘉泰姆

NEG1sYd嘉泰姆

NEG1sYd嘉泰姆

Inverting Input of Operational-Amplifier 1sYd嘉泰姆

7sYd嘉泰姆

POS1sYd嘉泰姆

POS1sYd嘉泰姆

POS1sYd嘉泰姆

Non-inverting Input of Operational-Amplifier 1sYd嘉泰姆

8sYd嘉泰姆

NCsYd嘉泰姆

OUT2sYd嘉泰姆

OUT2sYd嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalsYd嘉泰姆
connected of CXSU63137.sYd嘉泰姆

9sYd嘉泰姆

NCsYd嘉泰姆

NEG2sYd嘉泰姆

NEG2sYd嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalsYd嘉泰姆
connected of CXSU63137.sYd嘉泰姆

10sYd嘉泰姆

ICsYd嘉泰姆

POS2sYd嘉泰姆

POS2sYd嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. InternalsYd嘉泰姆
connected to GND of CXSU63137sYd嘉泰姆

11sYd嘉泰姆

BGNDsYd嘉泰姆

BGNDsYd嘉泰姆

BGNDsYd嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)sYd嘉泰姆
underneath the IC.sYd嘉泰姆

12sYd嘉泰姆

NCsYd嘉泰姆

NCsYd嘉泰姆

POS3sYd嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internalsYd嘉泰姆
connected of CXSU63137/CXSU63137.sYd嘉泰姆

13sYd嘉泰姆

NCsYd嘉泰姆

NCsYd嘉泰姆

OUT3sYd嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.sYd嘉泰姆

14sYd嘉泰姆

SUPsYd嘉泰姆

SUPsYd嘉泰姆

SUPsYd嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. BypasssYd嘉泰姆
SUP to BGND with a 0.1μF capacitor.sYd嘉泰姆

15sYd嘉泰姆

NCsYd嘉泰姆

POS3sYd嘉泰姆

POS4sYd嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertingsYd嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.sYd嘉泰姆

16sYd嘉泰姆

NCsYd嘉泰姆

NEG3sYd嘉泰姆

NEG4sYd嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofsYd嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.sYd嘉泰姆

17sYd嘉泰姆

NCsYd嘉泰姆

OUT3sYd嘉泰姆

OUT4sYd嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofsYd嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.sYd嘉泰姆

18sYd嘉泰姆

ICsYd嘉泰姆

ICsYd嘉泰姆

POS5sYd嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connectedsYd嘉泰姆
to GND of CXSU63137/CXSU63137.sYd嘉泰姆

19sYd嘉泰姆

NCsYd嘉泰姆

NCsYd嘉泰姆

NEG5sYd嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connectedsYd嘉泰姆
of CXSU63137/CXSU63137.sYd嘉泰姆

20sYd嘉泰姆

NCsYd嘉泰姆

NCsYd嘉泰姆

OUT5sYd嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.sYd嘉泰姆

21sYd嘉泰姆

LXsYd嘉泰姆

LXsYd嘉泰姆

LXsYd嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductorsYd嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.sYd嘉泰姆

22sYd嘉泰姆

INsYd嘉泰姆

INsYd嘉泰姆

INsYd嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can rangesYd嘉泰姆
from 2.6V to 6.5V.sYd嘉泰姆

23sYd嘉泰姆

FBsYd嘉泰姆

FBsYd嘉泰姆

FBsYd嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider fromsYd嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withinsYd嘉泰姆
5mm of FB.sYd嘉泰姆

24sYd嘉泰姆

COMPsYd嘉泰姆

COMPsYd嘉泰姆

COMPsYd嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCsYd嘉泰姆
from COMP to AGND.sYd嘉泰姆

PinFunction DescriptionsYd嘉泰姆

PinsYd嘉泰姆

NamesYd嘉泰姆

Function DescriptionsYd嘉泰姆

CXSU63137sYd嘉泰姆

CXSU63137-1sYd嘉泰姆

CXSU63137-2sYd嘉泰姆

24sYd嘉泰姆

COMPsYd嘉泰姆

COMPsYd嘉泰姆

COMPsYd嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCsYd嘉泰姆
from COMP to AGND.sYd嘉泰姆

25sYd嘉泰姆

FBPsYd嘉泰姆

FBPsYd嘉泰姆

FBPsYd嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of asYd嘉泰姆
resistive voltage-divider between the regulator output and AGND to set thesYd嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-dividersYd嘉泰姆
close to the pin.sYd嘉泰姆

26sYd嘉泰姆

DRVPsYd嘉泰姆

DRVPsYd嘉泰姆

DRVPsYd嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channelsYd嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.sYd嘉泰姆

27sYd嘉泰姆

FBNsYd嘉泰姆

FBNsYd嘉泰姆

FBNsYd嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of asYd嘉泰姆
resistive voltage-divider between the regulator output and REF to set thesYd嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-dividersYd嘉泰姆
close to the pin.sYd嘉泰姆

28sYd嘉泰姆

DRVNsYd嘉泰姆

DRVNsYd嘉泰姆

DRVNsYd嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channelsYd嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.sYd嘉泰姆

29sYd嘉泰姆

DELsYd嘉泰姆

DELsYd嘉泰姆

DELsYd嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND tosYd嘉泰姆
set the high-voltage switch startup delay.sYd嘉泰姆

30sYd嘉泰姆

CTLsYd嘉泰姆

CTLsYd嘉泰姆

CTLsYd嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchsYd嘉泰姆
between COM and SRC is on and the high-voltage switch between COM andsYd嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRCsYd嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL issYd嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thansYd嘉泰姆
1.25V.sYd嘉泰姆

31sYd嘉泰姆

DRNsYd嘉泰姆

DRNsYd嘉泰姆

DRNsYd嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channelsYd嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceedsYd嘉泰姆
VSRC.sYd嘉泰姆

32sYd嘉泰姆

COMsYd嘉泰姆

COMsYd嘉泰姆

COMsYd嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow thesYd嘉泰姆
voltage on COM to exceed VSRC.sYd嘉泰姆

六.电路原理图sYd嘉泰姆
七,功能概述sYd嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:sYd嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.sYd嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.sYd嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.sYd嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.sYd嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.sYd嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.sYd嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-upsYd嘉泰姆
八,相关产品sYd嘉泰姆

Switching Regulator > Boost ConvertersYd嘉泰姆

 Part_No sYd嘉泰姆

PackagesYd嘉泰姆

Archi-tecture sYd嘉泰姆

Input sYd嘉泰姆

Voltage    sYd嘉泰姆

Max Adj.sYd嘉泰姆

Output sYd嘉泰姆

Voltage sYd嘉泰姆

Switch Current Limit (max) sYd嘉泰姆

Fixed sYd嘉泰姆

Output sYd嘉泰姆

Voltage  sYd嘉泰姆

Switching sYd嘉泰姆

Frequency sYd嘉泰姆

Internal Power   Switch sYd嘉泰姆

Sync. Rectifier sYd嘉泰姆

 

minsYd嘉泰姆

maxsYd嘉泰姆

minsYd嘉泰姆

maxsYd嘉泰姆

(A)sYd嘉泰姆

(V)sYd嘉泰姆

(kHz)sYd嘉泰姆

 

CXSU63133sYd嘉泰姆

SOT89sYd嘉泰姆

VM sYd嘉泰姆

0.9sYd嘉泰姆

5.5sYd嘉泰姆

2.5sYd嘉泰姆

5.5sYd嘉泰姆

0.5sYd嘉泰姆

1.8|2.6|2.8|3sYd嘉泰姆

|3.3|3.8|4.5|5sYd嘉泰姆

-sYd嘉泰姆

NosYd嘉泰姆

YessYd嘉泰姆

CXSU63134sYd嘉泰姆

MSOP8|TSSOP8sYd嘉泰姆

|SOP8sYd嘉泰姆

VMsYd嘉泰姆

2.5sYd嘉泰姆

5.5sYd嘉泰姆

2.5sYd嘉泰姆

-sYd嘉泰姆

-sYd嘉泰姆

-sYd嘉泰姆

200 ~ 1000sYd嘉泰姆

NosYd嘉泰姆

NosYd嘉泰姆

CXSU63135sYd嘉泰姆

TSSOP8|SOP-8PsYd嘉泰姆

VMsYd嘉泰姆

1sYd嘉泰姆

5.5sYd嘉泰姆

2.5sYd嘉泰姆

5sYd嘉泰姆

1sYd嘉泰姆

2.5|3.3sYd嘉泰姆

300sYd嘉泰姆

YessYd嘉泰姆

YessYd嘉泰姆

CXSU63136sYd嘉泰姆

SOP8sYd嘉泰姆

CMsYd嘉泰姆

3sYd嘉泰姆

40sYd嘉泰姆

1.25sYd嘉泰姆

40sYd嘉泰姆

1.5sYd嘉泰姆

-sYd嘉泰姆

33 ~ 100sYd嘉泰姆

YessYd嘉泰姆

NosYd嘉泰姆

CXSU63137sYd嘉泰姆

TQFN5x5-32sYd嘉泰姆

CMsYd嘉泰姆

2.5sYd嘉泰姆

6.5sYd嘉泰姆

2.5sYd嘉泰姆

18sYd嘉泰姆

3sYd嘉泰姆

NosYd嘉泰姆

1200sYd嘉泰姆

YessYd嘉泰姆

NosYd嘉泰姆

CXSU63138sYd嘉泰姆

TSOT23-5sYd嘉泰姆

TDFN2x2-6sYd嘉泰姆

CMsYd嘉泰姆

2.5sYd嘉泰姆

6sYd嘉泰姆

2.5sYd嘉泰姆

20sYd嘉泰姆

2sYd嘉泰姆

-sYd嘉泰姆

1500sYd嘉泰姆

YessYd嘉泰姆

NosYd嘉泰姆

CXSU63139sYd嘉泰姆

TQFN4x4-6sYd嘉泰姆

TDFN3x3-12sYd嘉泰姆

CMsYd嘉泰姆

1.8sYd嘉泰姆

5.5sYd嘉泰姆

2.7sYd嘉泰姆

5.5sYd嘉泰姆

5sYd嘉泰姆

-sYd嘉泰姆

1.2sYd嘉泰姆

YessYd嘉泰姆

YessYd嘉泰姆

CXSU63140sYd嘉泰姆

SOT23-5sYd嘉泰姆

CMsYd嘉泰姆

2.5sYd嘉泰姆

6sYd嘉泰姆

2.5sYd嘉泰姆

32sYd嘉泰姆

1sYd嘉泰姆

-sYd嘉泰姆

1000sYd嘉泰姆

YessYd嘉泰姆

NosYd嘉泰姆

CXSU63141sYd嘉泰姆

TSOT-23-6 sYd嘉泰姆

TDFN2x2-8sYd嘉泰姆

CMsYd嘉泰姆

1.2sYd嘉泰姆

5.5sYd嘉泰姆

1.8sYd嘉泰姆

5.5sYd嘉泰姆

1.2sYd嘉泰姆

-sYd嘉泰姆

1.2sYd嘉泰姆

YessYd嘉泰姆

YessYd嘉泰姆

 sYd嘉泰姆

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