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首页 > 产品中心 > 电源管理 > DC降压型芯片 > Buck降压型芯片 >CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V
CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V
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CXSD62104集成了双降压、恒定时间、同步PWM控制器(为每个通道驱动双N通道mosfet)和
两个低损耗稳压器以及各种保护装置集成到一个芯片中。PWM控制器降低电池的高电压以产生NB的低电压应用。PWM1和PWM2的输出可以从2V调整到5.5V通过设置一个从VOUTx到GND的电阻分压器。线性调节器为备用电源提供5V和3.3V输出

CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V
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产品简介

目录1Ut嘉泰姆

1.产品概述                       2.产品特点1Ut嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 1Ut嘉泰姆
5.产品封装图                     6.电路原理图                   1Ut嘉泰姆
7.功能概述                        8.相关产品1Ut嘉泰姆

一,产品概述(General Description)         1Ut嘉泰姆

        The CXSD62104  integrates dual step-down, constant-ontime, synchronous1Ut嘉泰姆

PWM controllers (that drives dual N-channel MOSFETs for each channel) and1Ut嘉泰姆
two low drop-out regulators as well as various protections into a chip.The PWM1Ut嘉泰姆
controllers step down high voltage of a battery to generate low-voltage for NB1Ut嘉泰姆
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5V1Ut嘉泰姆
by setting a resistive voltage-divider from VOUTx to GND.The linear regulators1Ut嘉泰姆
provide 5V and 3.3V output for standby power supply. The linear regulators1Ut嘉泰姆

provide up to 100mA output current. When the PWMx output voltage is higher 1Ut嘉泰姆

than LDOx bypass threshold, the related LDOx regulator is shut off and its 1Ut嘉泰姆

output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.1Ut嘉泰姆
     The CXSD62104 provides excellent transient response and accurate DC 1Ut嘉泰姆

output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), 1Ut嘉泰姆

the CXSD62104 provides very high efficiency over light to heavy loads with 1Ut嘉泰姆

loading-modulated switching frequencies. The Forced-PWM mode works nearly 1Ut嘉泰姆

at constant frequency for low-noise requirements. The unique ultrasonic mode1Ut嘉泰姆

 maintains the switching frequency above 25KHz, which eliminates noise in audio applications.1Ut嘉泰姆

     The CXSD62104 is equipped with accurate sourcing cur-rent-limit, output1Ut嘉泰姆

under-voltage and output over-voltage protections, being perfect for NB 1Ut嘉泰姆

applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. 1Ut嘉泰姆

A soft-stop function actively discharges the output capaci-tors by the discharge 1Ut嘉泰姆

device. The CXSD62104 has individual enable controls for PWM channels and 1Ut嘉泰姆

LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chip1Ut嘉泰姆

with low quiescent current close to zero.1Ut嘉泰姆
      The CXSD62104 is available in a TQFN4x4-24A package.1Ut嘉泰姆
二.产品特点(Features)1Ut嘉泰姆
Wide Input Voltage Range from 6V to 25V1Ut嘉泰姆
Provide 4 Independent Outputs with ±1.5% Accu-1Ut嘉泰姆
racy Over-Temperature1Ut嘉泰姆
- PWM1 Controller with Adjustable (2V to 5.5V) Out-put1Ut嘉泰姆
PWM2 Controller with Adjustable (2V to 5.5V) Out-put1Ut嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V Output1Ut嘉泰姆
100mA Low Dropout Regulator (LDO3) with Fixed 3.3V Output1Ut嘉泰姆
Excellent Line/Load Regulations about ±1.5% Over-Temperature Range1Ut嘉泰姆
±1%, (±1.5%, 50μA) 2.0V Reference Voltage Output1Ut嘉泰姆
Built-In POR Control Scheme Implemented1Ut嘉泰姆
Selectable Forced-PWM or Automatic PFM/PWM1Ut嘉泰姆
(with Selectable Ultrasonic Operation)1Ut嘉泰姆
Constant-On-Time Control Scheme with Frequency1Ut嘉泰姆
Compensation for PWM Mode1Ut嘉泰姆
Selectable Switching Frequency in PWM Mode1Ut嘉泰姆
Built-in Digital Soft-Start for PWM Outputs and Soft-1Ut嘉泰姆
Stop for PWM Outputs and LDO Outputs1Ut嘉泰姆
Integrated Bootstrap Forward P-CH MOSFET1Ut嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)1Ut嘉泰姆
Built-in Power Good Indicators (PWMs)1Ut嘉泰姆
Independent Enable Inputs (PWMs, LDO)1Ut嘉泰姆

70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM)1Ut嘉泰姆

Adjustable Current-Limit Protection (PWMs)1Ut嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)1Ut嘉泰姆
Over-Temperature Protection1Ut嘉泰姆
4mmx4mm Thin QFN-24 (TQFN4x4-24A) package1Ut嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)
1Ut嘉泰姆

三,应用范围 (Applications)1Ut嘉泰姆

Notebook and Sub-Notebook Computers1Ut嘉泰姆

Portable Devices1Ut嘉泰姆
DDR1, DDR2, and DDR3 Power Supplies1Ut嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered Devices1Ut嘉泰姆
Graphic Cards1Ut嘉泰姆
Game Consoles1Ut嘉泰姆
Telecommunications
1Ut嘉泰姆

四.下载产品资料PDF文档 1Ut嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持1Ut嘉泰姆

 QQ截图20160419174301.jpg1Ut嘉泰姆

五,产品封装图 (Package)1Ut嘉泰姆


blob.pngblob.png1Ut嘉泰姆

六.电路原理图1Ut嘉泰姆


blob.png1Ut嘉泰姆

七,功能概述1Ut嘉泰姆


Input Capacitor Selection1Ut嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select1Ut嘉泰姆
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS1Ut嘉泰姆
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors are1Ut嘉泰姆
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-1Ut嘉泰姆
side MOSFET with very low-impeadance PCB layout. 1Ut嘉泰姆
MOSFET Selection1Ut嘉泰姆
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs should1Ut嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:1Ut嘉泰姆
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFET1Ut嘉泰姆
driver will not charge the miller capacitor of this MOSFET.1Ut嘉泰姆
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. The1Ut嘉泰姆
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver1Ut嘉泰姆
sinking current path. This results in much less switching loss of the low-side MOSFETs. The duty1Ut嘉泰姆
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-1Ut嘉泰姆
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the power1Ut嘉泰姆
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET1Ut嘉泰姆
does not have this zero voltage switching condition, and because it conducts for less time1Ut嘉泰姆
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given1Ut嘉泰姆
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.1Ut嘉泰姆
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitance1Ut嘉泰姆
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-1Ut嘉泰姆
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given by1Ut嘉泰姆
the following equations:1Ut嘉泰姆
Layout Consideration1Ut嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.1Ut嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across1Ut嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition1Ut嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,1Ut嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasitic1Ut嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and1Ut嘉泰姆
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. And1Ut嘉泰姆
signal and power grounds are to be kept separating and finally combined to use the ground plane construction or1Ut嘉泰姆

single point grounding. The best tie-point between the signal ground and the power ground is at the negative1Ut嘉泰姆
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not1Ut嘉泰姆
recommended. Below is a checklist for your layout:1Ut嘉泰姆
Layout Consideration (Cont.)1Ut嘉泰姆
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodes1Ut嘉泰姆
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes as1Ut嘉泰姆
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.1Ut嘉泰姆

Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce of1Ut嘉泰姆

CXSD621041Ut嘉泰姆

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TDFN3x3-101Ut嘉泰姆

VM1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

251Ut嘉泰姆

41Ut嘉泰姆

13.21Ut嘉泰姆

0.81Ut嘉泰姆

5~121Ut嘉泰姆

20001Ut嘉泰姆

CXSD62981Ut嘉泰姆

TDFN3x3-101Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

251Ut嘉泰姆

4.51Ut嘉泰姆

251Ut嘉泰姆

0.61Ut嘉泰姆

5~121Ut嘉泰姆

801Ut嘉泰姆

CXSD6299|A1Ut嘉泰姆

SOP-8P1Ut嘉泰姆

VM1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

251Ut嘉泰姆

4.51Ut嘉泰姆

13.21Ut嘉泰姆

0.81Ut嘉泰姆

5~121Ut嘉泰姆

160001Ut嘉泰姆

CXSD621001Ut嘉泰姆

TQFN3x3-101Ut嘉泰姆

VM1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

251Ut嘉泰姆

4.51Ut嘉泰姆

13.21Ut嘉泰姆

0.61Ut嘉泰姆

5~121Ut嘉泰姆

25001Ut嘉泰姆

CXSD62101|L1Ut嘉泰姆

TDFN3x3-101Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

301Ut嘉泰姆

31Ut嘉泰姆

251Ut嘉泰姆

0.81Ut嘉泰姆

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20001Ut嘉泰姆

CXSD621021Ut嘉泰姆

TQFN3x3-161Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

301Ut嘉泰姆

1.81Ut嘉泰姆

281Ut嘉泰姆

0.61Ut嘉泰姆

51Ut嘉泰姆

6001Ut嘉泰姆

CXSD62102A1Ut嘉泰姆

TQFN 3x3 161Ut嘉泰姆

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11Ut嘉泰姆

11Ut嘉泰姆

301Ut嘉泰姆

1.81Ut嘉泰姆

281Ut嘉泰姆

0.61Ut嘉泰姆

51Ut嘉泰姆

6001Ut嘉泰姆

CXSD621031Ut嘉泰姆

QFN4x4-241Ut嘉泰姆

VM1Ut嘉泰姆

21Ut嘉泰姆

11Ut嘉泰姆

501Ut嘉泰姆

4.51Ut嘉泰姆

13.21Ut嘉泰姆

0.61Ut嘉泰姆

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50001Ut嘉泰姆

CXSD621041Ut嘉泰姆

TQFN4x4-241Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

21Ut嘉泰姆

151Ut嘉泰姆

61Ut嘉泰姆

251Ut嘉泰姆

21Ut嘉泰姆

N1Ut嘉泰姆

5501Ut嘉泰姆

CXSD621051Ut嘉泰姆

TQFN4x4-241Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

21Ut嘉泰姆

151Ut嘉泰姆

61Ut嘉泰姆

251Ut嘉泰姆

21Ut嘉泰姆

N1Ut嘉泰姆

5501Ut嘉泰姆

CXSD62106|A1Ut嘉泰姆

TQFN4x4-41Ut嘉泰姆

TQFN3x3-201Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

21Ut嘉泰姆

201Ut嘉泰姆

31Ut嘉泰姆

281Ut嘉泰姆

0.751Ut嘉泰姆

51Ut嘉泰姆

8001Ut嘉泰姆

CXSD621071Ut嘉泰姆

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281Ut嘉泰姆

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CXSD621081Ut嘉泰姆

QFN3.5x3.5-141Ut嘉泰姆

TQFN3x3-161Ut嘉泰姆

COT1Ut嘉泰姆

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CXSD621091Ut嘉泰姆

TQFN3x3-161Ut嘉泰姆

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201Ut嘉泰姆

1.81Ut嘉泰姆

281Ut嘉泰姆

0.751Ut嘉泰姆

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CXSD621101Ut嘉泰姆

QFN3x3-201Ut嘉泰姆

TQFN3x3-161Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

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201Ut嘉泰姆

31Ut嘉泰姆

281Ut嘉泰姆

1.8|1.5|0.51Ut嘉泰姆

51Ut嘉泰姆

7401Ut嘉泰姆

CXSD621111Ut嘉泰姆

TQFN4x4-241Ut嘉泰姆

|QFN3x3-201Ut嘉泰姆

CM1Ut嘉泰姆

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151Ut嘉泰姆

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281Ut嘉泰姆

0.51Ut嘉泰姆

N1Ut嘉泰姆

30001Ut嘉泰姆

CXSD621121Ut嘉泰姆

TDFN3x3-101Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

201Ut嘉泰姆

1.81Ut嘉泰姆

281Ut嘉泰姆

0.51Ut嘉泰姆

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2501Ut嘉泰姆

CXSD62113|C1Ut嘉泰姆

TQFN3x3-201Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

21Ut嘉泰姆

151Ut嘉泰姆

61Ut嘉泰姆

251Ut嘉泰姆

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N1Ut嘉泰姆

5501Ut嘉泰姆

CXSD62113E1Ut嘉泰姆

TQFN 3x3 201Ut嘉泰姆

COT1Ut嘉泰姆

21Ut嘉泰姆

21Ut嘉泰姆

111Ut嘉泰姆

61Ut嘉泰姆

251Ut嘉泰姆

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N1Ut嘉泰姆

5501Ut嘉泰姆

CXSD621141Ut嘉泰姆

TQFN3x3-201Ut嘉泰姆

COT1Ut嘉泰姆

21Ut嘉泰姆

21Ut嘉泰姆

111Ut嘉泰姆

5.51Ut嘉泰姆

251Ut嘉泰姆

21Ut嘉泰姆

N1Ut嘉泰姆

2801Ut嘉泰姆

CXSD621151Ut嘉泰姆

QFN4x4-241Ut嘉泰姆

VM1Ut嘉泰姆

21Ut嘉泰姆

11Ut嘉泰姆

601Ut嘉泰姆

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13.21Ut嘉泰姆

0.851Ut嘉泰姆

121Ut嘉泰姆

50001Ut嘉泰姆

CXSD62116A|B|C1Ut嘉泰姆

SOP-8P1Ut嘉泰姆

VM1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

201Ut嘉泰姆

2.91Ut嘉泰姆

13.21Ut嘉泰姆

0.81Ut嘉泰姆

121Ut嘉泰姆

160001Ut嘉泰姆

CXSD621171Ut嘉泰姆

SOP-201Ut嘉泰姆

VM1Ut嘉泰姆

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21Ut嘉泰姆

301Ut嘉泰姆

101Ut嘉泰姆

13.21Ut嘉泰姆

11Ut嘉泰姆

121Ut嘉泰姆

50001Ut嘉泰姆

CXSD621181Ut嘉泰姆

TDFN3x3-101Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

11Ut嘉泰姆

251Ut嘉泰姆

1.81Ut嘉泰姆

281Ut嘉泰姆

0.71Ut嘉泰姆

51Ut嘉泰姆

2501Ut嘉泰姆

CXSD621191Ut嘉泰姆

TQFN3x3-201Ut嘉泰姆

COT1Ut嘉泰姆

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11Ut嘉泰姆

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1.81Ut嘉泰姆

251Ut嘉泰姆

REFIN Setting1Ut嘉泰姆

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CXSD621201Ut嘉泰姆

QFN 3x3 201Ut嘉泰姆

TQFN 3x3 161Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

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201Ut嘉泰姆

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281Ut嘉泰姆

1.8|1.5 1.35|1.2 0.51Ut嘉泰姆

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8001Ut嘉泰姆

CXSD62121A1Ut嘉泰姆

TQFN3x3 201Ut嘉泰姆

COT1Ut嘉泰姆

11Ut嘉泰姆

21Ut嘉泰姆

151Ut嘉泰姆

31Ut嘉泰姆

281Ut嘉泰姆

0.751Ut嘉泰姆

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2201Ut嘉泰姆

CXSD62121B1Ut嘉泰姆

TQFN3x3 201Ut嘉泰姆

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281Ut嘉泰姆

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CXSD621211Ut嘉泰姆

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281Ut嘉泰姆

0.751Ut嘉泰姆

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1801Ut嘉泰姆

 1Ut嘉泰姆

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